Semiconductor device

ABSTRACT

A semiconductor device has a circuit element having a given value of a characteristic property. The circuit element has at least two individual elements, each having an individual value for the characteristic value thereof, the individual values including an error portion that is substantially statistically uncorrelated, the individual elements disposed solely for contributing to the values of the characteristic property.

FIELD OF THE INVENTION

The instant invention relates to semiconductor devices having enhancedintrinsic precision properties that allow establishing a characteristiclength in the sub-μm region.

BACKGROUND OF THE INVENTION

One of the major goals in modern telecommunication is to achieve everincreasing transmission rates as well as data broadcast speeds, which isintimately coupled with the need of new and advanced technologiesproviding the necessary tools for accomplishing this quest. The demandfor high precision in manufacturing semiconductor devices calls for thedevelopment of new manufacture tools and technologies, which isaccompanied with a considerable amount of financial efforts. Thus, itwould be advantageous to have at hand simple concepts which allow forthe production of semiconductor devices with a characteristic lengthwell below the μm region, but which do not require additional operatingexpenses.

SUMMARY OF THE INVENTION

In accordance with the invention there is provided a semiconductordevice comprising: a circuit element having a given value of acharacteristic property and comprising: at least two individualelements, each having an individual value for the characteristic valuethereof, the individual values including an error portion that issubstantially statistically uncorrelated, the individual elementsdisposed solely for contributing to the values of the characteristicproperty.

In accordance with another aspect the invention there is provided amethod of providing a design of a semiconductor device comprising:providing a design of a circuit for inclusion within the semiconductordevice, the circuit including a high precision circuit element having afirst characteristic value; forming the high precision circuit elementfrom a plurality of individual circuit elements having characteristicvalues other than the first characteristic value arranged for providinga concatenated circuit element having the first characteristic value;and, providing an electronic design including the concatenated circuitelement and having the individual circuit elements arranged forresulting in errors in the manufacturing thereof, the errors beingsubstantially other than correlated one with another.

In accordance with another aspect the invention there is provided astorage medium having instruction data stored therein for when executingby a processor resulting in performance of: providing a design of acircuit for inclusion within the semiconductor device, the circuitincluding a high precision circuit element having a first characteristicvalue; forming the high precision circuit element from a plurality ofindividual circuit elements having characteristic values other than thefirst characteristic value arranged for providing a concatenated circuitelement having the first characteristic value; and, providing anelectronic design including the concatenated circuit element and havingthe individual circuit elements arranged for resulting in errors in themanufacturing thereof, the errors being substantially other thancorrelated one with another.

BRIEF DESCRIPTION OF THE DRAWINGS

The instant invention is now described in detail in conjunction with thefollowing drawings, in which

FIG. 1 shows part of a prior art conventional semiconductor device;

FIG. 2 shows an embodiment of part of a semiconductor device;

FIG. 3 shows an embodiment of part of a semiconductor device;

FIG. 3 b shows a simplified graphical diagram of error distributionwithin a manufacturing process;

FIG. 4 shows an embodiment of part of a semiconductor device;

FIG. 5 shows a simplified flow diagram of a method according to thepresent invention; and

FIG. 6 shows a simplified flow diagram of a method according to thepresent invention.

DETAILED DESCRIPTION OF THE INVENTION

In FIG. 1, a schematic partial diagram of a prior art semiconductordevice 100 is shown. The semiconductor devices is manufactured in theusual way, and comprises different layers of different materials, intowhich by means of deposition, masking, etching, and/or other productiontechniques various elements are integrated. The semiconductor devicecomprises a variety of different elements, such as resistors,capacitors, transistors, diodes, and the like, two of which areschematically displayed in FIG. 1. Theses elements are designated as Q₁and Q₂, and referred to as 101 and 102. An element Q_(n) in the form ofa resistor possesses characteristic dimensions, which are, for theresistor, characteristic length L_(n), characteristic width W_(n), andcharacteristic height H_(n). The characteristic length L_(n) of theelement extends in a direction substantially parallel to the currentflow through the element Q_(n), and direction of characteristic widthW_(n) together with the direction of characteristic length L_(n) definea set of vectors that span a two-dimensional plane perpendicular to thedirection of current flow within the element Q_(n), of the semiconductordevice 100.

Each element possesses a characteristic property such as resistance,capacitance, inductance, and so forth. The characteristic property ofelement Q_(n) is in the following designated as Θ_(n). For asemiconductor device, Θ_(n) typically is a function of thecharacteristic length L_(n) of element Q_(n), equation (1):Θ_(n) =f(L _(n))  (1)

Associated with each characteristic property Θ_(n) is associated acertain error ΔΘ_(n), defining the accuracy of element Q_(n). Similar toequation (1), the error ΔΘ_(n) is expressed as a function of fabricationprecision ΔL_(n), equation (2):ΔΘ_(n) =f(ΔL _(n))  (2)

In order to achieve a certain performance precision, allowing for anincrease in speed and for a dimension reduction into the sub-em region,an enhanced precision, that is a smaller ΔL_(n), is desirable. That inmany cases calls for enhanced manufacturing techniques, allowing formore precise production of semiconductor devices.

Referring now to FIG. 2, shown is a schematic diagram of a semiconductordevice 200 including an RC circuit according to the instant invention.The semiconductor device according to the instant invention ismanufactured using known technologies and in similar fashion asdescribed above. The semiconductor device comprises a resistor 201 and aconcatenated element Q_(c) forming a capacitance of the RC circuit. Aconcatenated element Q_(c) 201 comprises ten individual elements Q₀ 210to Q₉ 219, respectively. Referring to FIG. 2, these elements areconnected in series. Other arrangements are easily envisioned, in whichfor example the elements Q₀ 210 to Q₉ 219 are connected in parallel.

The principle of the instant invention is now illustrated for acapacitor with capacitance C comprising ten individual capacitors withcapacitances C₀ to C₉, respectively, the ten individual capacitorsconnected in parallel. A person of skill in the art with ease extendsthis example to other representative elements as well.

The capacitance C of a capacitor on a semiconductor device is basicallyexpressed by equation (3): $\begin{matrix}{C = {ɛ_{0} \cdot ɛ_{r} \cdot \frac{W}{H} \cdot L}} & (3)\end{matrix}$

In equation (3), ε₀ is the dielectric constant in vacuo, and ε_(r) amaterial dependent dielectric constant of the semiconductor device.Assuming that the ten individual capacitors have constant height andconstant width, and combining the constant values of W, H, ε₀ and ε_(r)into a new constant κ, one obtains:C=κ·L  (4)

Since the ten individual capacitors are connected in parallel, oneobtains the following relation between capacitance and individuallengths: $\begin{matrix}{C = {{\sum\limits_{n = 0}^{9}C_{n}} = {\kappa \cdot {\sum\limits_{n = 0}^{9}L_{n}}}}} & (5)\end{matrix}$

Equation (5) in view of equation (3) suggests that the precision incapacitance C is directly related to the accuracy with which theindividual capacitors are manufactured. If the ten individual capacitorsare manufactured in a statistically correlated fashion, that is if theyare manufactured within the same process, the precision in capacitanceΔC is a sum of the absolute values of fabrication precision:$\begin{matrix}{{\Delta\quad C} = {{\sum\limits_{n = 0}^{9}{{\Delta\quad L_{n}}}} = {10\delta}}} & (6)\end{matrix}$

In equation 6, δ represents an absolute value of a fabrication precisionΔL_(n). In case that the ten individual capacitors are not manufacturedwith a same process, their individual errors are truly uncorrelated, andone obtains: $\begin{matrix}{{\Delta\quad C} = {\sum\limits_{n = 0}^{9}{{\pm \Delta}\quad L_{n}}}} & (7)\end{matrix}$

According to the instant invention, the semiconductor device ismanufactured in a way that the individual elements constituting a givenelement Q_(n) are manufactured independently, and are therefore notstatistically correlated. Thus, the fabrication precision ΔL_(n) isdifferent for all individual elements, possibly not only in magnitude,but also in sign. This allows for error cancellation resulting in aconcatenated element Q_(c) with a higher precision in its characteristicproperty than a single element Q having essentially the same value forΘ.

Statistical correlation is avoidable through numerous methods. One ofskill in the art will appreciate that differing levels of statisticaldecorrelation result in improved or reduced benefit of the inventivemethod disclosed herein.

Referring to FIG. 3, a portion of a schematic for a semiconductor device300 according to the invention is shown wherein the individual elementsconstituting a given element Q_(n) are specified distinctly and aretherefore not statistically correlated. Here, each individual elementhas a different characteristic value differing from the others by anamount selected to be statistically distinct. For example, as shown, byselecting lengths of the capacitive elements that vary in small amountsbut result in capacitances that sum to the overall desired capacitance,a further correlation between individual elements is eliminated. Forexample, when the capacitances are 10.02, 9.83, 10.08, 10.11, 9.96, theerror within each capacitance value is substantially uncorrelated as theerrors relating to process vary due to the small variations inindividual capacitor sizes. If the capacitive elements are alsomanufactured according to a different process—disposed on differentlayers or manufactured differently—then two types of decorrelationbetween individual errors result. Increasing the types of decorrelationacts to increase the convolution of error functions resulting in alarger proportion of errors being grouped about the desired value andfewer errors being distant therefrom (convolution of two peaks resultsin a sharper peak as shown in FIG. 3 b).

Referring to FIG. 3 b, a graph is shown having two curves. The curve 351is a statistical distribution of random error for manufacturing of asingle element. When two elements forming a concatenated element aremanufactured with statistically uncorrelated processes, the resultingerror distribution has a sharper peak thereby reducing the number ofresulting concatenated elements falling outside a given accuracy. Thoughthis is the case, the maximum error value resulting from themanufacturing process remains unchanged. Greater number of elementsforming the concatenated element and each formed such that the error inthe manufacture thereof is uncorrelated with the error within themanufacture of the other elements results in an even sharper peak andtherefore in a tighter grouping of the concatenated element about adesignated value.

As the level of correlation between individual elements is reduced, theportion of the manufacturing error that is able to cancel with othererrors becomes increased for the set of individual elements. Thus, thelevel or percentage of repeatability in manufacture is enhanced throughthe present process. The present method allows for a tighter grouping oferrors about a near zero error value therefore increasing yield or, forhigh precision components, manufacturability.

Here, the capacitance of the individual elements instead of being thetotal capacitance divided by the number of individual elements is (thetotal capacitance divided by the number of individual elements) offsetby a small but significant amount. Of course, statistics are used todetermine significance. As such, when applied to the schematic in theexample of FIG. 2, each individual capacitor is slightly different butthe sum of all the capacitors is the capacitance C.

Referring to FIG. 4, a semiconductor device according to the inventionis shown wherein the individual elements constituting a given elementQ_(n) are specified distinctly and formed within different manufacturingsteps. Here, each individual element has a different characteristicvalue differing from the others by an amount selected to bestatistically distinct, for example 10.00, 11.12, and 8.88, and eachindividual element is disposed on a different layer or formed by aseparate process, for example, using different dielectrics. As such, thelevel of correlation between individual elements is reduced both indimension and in manufacturing resulting in the portion of themanufacturing error that is uncorrelated becoming increased for the setof individual elements. Conversely, correlated errors typically sumsimilarly for each additional element. Thus, when error is highlycorrelated, the resulting peak is similar regardless of the number ofelements.

Referring to FIG. 5, a flow diagram of a method according to theinvention is shown. A circuit is designed and provided for layout. Inthe layout process, circuit elements requiring high precision areidentified and are then divided into a plurality of individual elements,the plurality of individual elements having a same characteristic as theidentified circuit element requiring high precision. The individualelements are disposed within the layout in a manner to provide for astatistical decorrelation between manufacturing errors anticipated tooccur for each individual element. Preferably, the statisticaldecorrelation is sufficient to improve the efficiency to or above therequired high precision. The layout is then provided for manufactureand, during manufacture testing is performed to ensure that the increasein parts meeting or exceeding the required high precision is achieved.

It is well known to those of skill in the art that the method of FIG. 5is implementable manually or by an automated software process. Further,the process is implementable during design by the designer or by thesoftware tools used during design. Of course, implementing of the methodduring design in an automated fashion allows for simulation of thedesign as implemented providing increased testing abilities.

Decorrelation between errors induced in manufacture of individualelements is determinable through experimentation or through reasonableprediction. For example, elements formed by distinct processes, formedon different layers or with different masks, formed of differentcompositions, having distinct values, etc. typically result in smallercorrelation between manufacturing errors therebetween. Of course, thismay not always be the case.

Referring to FIG. 6, a flow diagram of a method according to theinvention is shown. A circuit is designed and provided for layout. Inthe layout process, circuit elements requiring high precision areidentified and are then divided into a plurality of individual elements,the plurality of individual elements having a same characteristic as theidentified circuit element requiring high precision. The individualelements are disposed within the layout in a manner to provide for astatistical decorrelation between manufacturing errors anticipated tooccur for each individual element. Preferably, the statisticaldecorrelation is sufficient to improve the efficiency to or above therequired high precision. The layout is then provided for simulation.Upon completion of the simulation, the design is modified as necessaryand then the process is iterated until the design requirements are met.The layout is then provided for manufacture and, during manufacturetesting is performed to ensure that the increase in parts meeting orexceeding the required high precision is achieved.

Although the present invention has been described with respect tospecific embodiments thereof, various changes and modifications areoptionally carried out by those skilled in the art without departingfrom the scope of the invention. Therefore, it is intended that thepresent invention encompass such changes and modifications as fallwithin the scope of the appended claims.

1. A semiconductor device comprising: a circuit element having a givenvalue of a characteristic property and comprising: at least twoindividual elements, each having an individual value for thecharacteristic value thereof, the individual values including an errorportion that is substantially statistically uncorrelated, the individualelements disposed solely for contributing to the values of thecharacteristic property.
 2. A semiconductor device according to claim 1,wherein the individual elements are members of the group consisting ofresistors, capacitors, and inductors.
 3. A semiconductor deviceaccording to claim 1 wherein the individual elements each have differentindividual values that differ one from another.
 4. A semiconductordevice according to claim 1 wherein the difference between individualvalues is less than 10 percent.
 5. A semiconductor device according toclaim 1 wherein there are more than 5 individual elements forming asingle concatenated element.
 6. A semiconductor device according toclaim 1 wherein some of the individual elements forming a sameconcatenated element are formed with different manufacturing processes.7. A semiconductor device according to claim 1 wherein some of theindividual elements forming a same concatenated element are dopeddifferently.
 8. A semiconductor device according to claim 6 wherein someof the individual elements forming a same concatenated element aredifferent types of a same element.
 9. A semiconductor device accordingto claim 6 wherein some of the individual elements forming a sameconcatenated element include different materials.
 10. A semiconductordevice according to claim 1 wherein some of the individual elementsforming a same concatenated element are formed with a same manufacturingprocess in a fashion that the manufacturing errors are uncorrelatedtherebetween.
 11. A semiconductor device according to claim 10 whereinsome of the individual elements forming a same concatenated element aredoped differently.
 12. A semiconductor device according to claim 10wherein some of the individual elements forming a same concatenatedelement are disposed within different layers of the semiconductordevice.
 13. A semiconductor device according to claim 1 wherein asubstantial portion of manufacturing errors of the individual elementsforming a same concatenated element are substantially uncorrelated inmore than one dimension.
 14. A semiconductor device according to claim13 wherein a substantial portion of manufacturing errors of theindividual elements forming a same concatenated element aresubstantially uncorrelated in more than two dimensions.
 15. A method ofproviding a design of a semiconductor device comprising: providing adesign of a circuit for inclusion within the semiconductor device, thecircuit including a high precision circuit element having a firstcharacteristic value; forming the high precision circuit element from aplurality of individual circuit elements having characteristic valuesother than the first characteristic value arranged for providing aconcatenated circuit element having the first characteristic value; and,providing an electronic design including the concatenated circuitelement and having the individual circuit elements arranged forresulting in errors in the manufacturing thereof, the errors beingsubstantially other than correlated one with another.
 16. A methodaccording to claim 15 comprising: manufacturing the semiconductor devicebased on the electronic design.
 17. A method according to claim 16comprising: simulating the electronic design; and amending one of theelectronic design and design of a circuit.
 18. A method according toclaim 15 comprising: i) simulating the electronic design; and ii)amending one of the electronic design and design of a circuit. Iterating(i) and (ii) until the simulated electronic design meets predetermineddesign criteria.
 19. A method according to claim 15 wherein the highprecision circuit element is formed of individual elements each havingdifferent individual values that differ one from another.
 20. A methodaccording to claim 19 wherein the difference between individual valuesis less than 10 percent.
 21. A method according to claim 19 wherein aremore than 5 individual elements form a single concatenated element. 22.A method according to claim 15 wherein some of the individual elementsforming a same concatenated element are for being formed with differentmanufacturing processes.
 23. A method according to claim 15 wherein someof the individual elements forming a same concatenated element are forbeing doped differently.
 24. A method according to claim 15 wherein someof the individual elements forming a same concatenated element are forbeing formed using a same manufacturing process in a fashion that themanufacturing errors are uncorrelated therebetween.
 25. A methodaccording to claim 15 wherein some of the individual elements forforming a same concatenated element are for being disposed withindifferent layers of the semiconductor device.
 26. A method according toclaim 15 wherein a substantial portion of manufacturing errors of theindividual elements forming a same concatenated element aresubstantially uncorrelated in more than one dimension.
 27. A methodaccording to claim 26 wherein a substantial portion of manufacturingerrors of the individual elements forming a same concatenated elementare substantially uncorrelated in more than two dimensions.
 28. Astorage medium having instruction data stored therein for when executingby a processor resulting in performance of: providing a design of acircuit for inclusion within the semiconductor device, the circuitincluding a high precision circuit element having a first characteristicvalue; forming the high precision circuit element from a plurality ofindividual circuit elements having characteristic values other than thefirst characteristic value arranged for providing a concatenated circuitelement having the first characteristic value; and, providing anelectronic design including the concatenated circuit element and havingthe individual circuit elements arranged for resulting in errors in themanufacturing thereof, the errors being substantially other thancorrelated one with another.
 29. A storage medium according to claim 28having instruction data stored therein for when executing by a processorwherein forming the high precision circuit element from a plurality ofindividual circuit elements includes a step of firming the highprecision circuit element from a plurality of individual circuitelements each having a different value of the characteristic valuethereof.